Variable electronic shutter in CMOS imager with improved anti smearing techniques

ABSTRACT

A leakage compensated snapshot imager provides a number of different aspects to prevent smear and other problems in a snapshot imager. The area where the imager is formed may be biased in a way that prevents photo carriers including electrons and holes from reaching a storage area. In addition, a number of different aspects may improve the efficiency. The capacitance per unit area of the storage area may be one, two or more orders of magnitude greater than the capacitance per-unit area of the photodiode. In addition, a ratio between photodiode capacitance and storage area capacitance is maintained larger than 0.7.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority from application Ser. No.60/210,295, filed Jun. 8, 2000.

BACKGROUND OF INVENTION

[0002] Electronically shuttered imagers have been implemented usingvarious image sensor technologies. For example, interline transfercharge coupled devices, CMOS active pixels, and pinned photodiode activepixels have been used for forming electronically shuttered imagers.

[0003] Many of these imagers may suffer from interframe smear and motionartifacts.

[0004] In addition, it may be desirable to provide the ability toprogram exposure time of such a device. The programmability may beprogrammable down to a level of a fraction of the frame readout time.This may operate to faithfully reproduce fast motion such as in sportsphotography.

SUMMARY OF INVENTION

[0005] The present application teaches a CMOS photodiode imager thatprovides snapshot imaging with electronic shutting and that may avoidsmearing.

[0006] In an embodiment, all pixel values may be stored simultaneously,and the image is obtained by reading these out row by row. A specialpixel cell redesign may take into account the causes of previousinterframe smearing and motion artifacts.

[0007] In an embodiment, optical and diffusion shields for the in pixelstorage part are provided. These shields may prevent leakage of chargefrom other areas into the in pixel storage part.

[0008] In addition, the effective photodiode and storage capacitance maybe optimized in order to improve signal swing and lower the noise. Theoptimization may be carried out according to a ratio of optimumrelationships between device capacitances. The disclosed pixelarchitecture may allow the in pixel capacitor to be implemented with aminimal impact on the fill factor.

[0009] Advantages may include high fidelity and reduction ofmotion-related artifact, reduced leakage into the in pixel memory, thusminimizing the smearing effect during imaging, programmable exposuretime independent of frame readout time, and high quantum efficiencyimaging. In addition, this system may produce a low noise output.

[0010] An aspect defines smear-free snapshot imaging is obtained whilemaintaining high quantum efficiency and low noise. This may be due tothe use of a storage capacitor with much higher per-unit capacitance.

BRIEF DESCRIPTION OF DRAWINGS

[0011] These and other aspects will now be described in detail withreference to the accompanying drawings, wherein: FIG. 1 shows a pixelarray including a detailed diagram of a single pixel; FIG. 2 shows across section of layers forming a photodiode; and FIG. 3 shows a ratiograph for the values of α.

DETAILED DESCRIPTION

[0012] Imaging sensors with in pixel memories are known. However, thepresent inventors realize that the interframe smear and motion artifactmay be due, at least partly, to seepage of charge from other areas, intothe in-pixel memory. The charge may include charge that is left overfrom other exposure times, for example.

[0013] For example, if there is a 5 percent leakage into the memory partof the chip, there is a 20:1 ratio between frame readout time andexposure time. This may result in a 50 percent unwanted signal. This cancorrespondingly cause image smear. To the extent that the unwantedsignal is representative of other exposure times, it may also introducemotion artifact.

[0014] A snapshot imager is shown in FIG. 1. The basic embodimentincludes an array of photoreceptors. A single photoreceptor 100 isshown, with the rest of the array being shown generically as 150.

[0015] Photoreceptor 100 is shown in a circuit with a pixel amplifier110. In the embodiment, the photoreceptor 100 may be a photodiode. Astorage capacitance 115 is placed in parallel with the photoreceptor100. The storage capacitance 115 may act as both a frame buffer memory,and as the sensing node.

[0016] The photodiode 100 is held in reset by closing the reset switch118, to connect the photodiode to the reset voltage 120. The photodiode100 operates to convert incoming photons to electrons (photoelectrons)for a specified amount of exposure time. The exposure time is defined bythe length of the interval during which the reset signal is held inreset.

[0017] The storage capacitance is analogously reset by closing the resetswitch 125. In an embodiment, the storage capacitance 115 may be resetafter the exposure, by pulsing the switch 125 into its closed position.After that, charge from the photodiode 100 may be simultaneouslytransferred into the storage capacitance by pulsing the “share” switch130.

[0018] The charge may be simultaneously transferred from all thedifferent photoreceptors of the array, into all of the different storagecapacitances 115 in all of the pixels 150 in the array. Since all of thephotoreceptors are sampled at the same time, a snapshot of the entirearray is taken at this one time. The charge may be read out row by row,but the charge that is read out is all representative of a single-timesnapshot image.

[0019] The exposure time may be varied independently by choosing theduration during which the reset level 118 is held low.

[0020] Once the charge from the photodiode has been transferred into thecapacitance 115 is complete, the photodiode may be reset and then begina new frame exposure. Values stored on the in pixel frame memory areagain scanned and out row at a time just as would occur in aconventional CMOS image sensor.

[0021] A number of issues are considered in a snapshot imager of thistype. It is desirable to vary the exposure time which, as describedabove, is possible in the FIG. 1 circuit. In addition, smear hasoccurred in such circuits, which the present inventors believes is dueto charge leakage into the capacitor 115. At least part of this leakageis from image acquisitions from previous integration times. The leakagemay result from an unwanted collection of photoelectrons via lateraldiffusion from the photodiode 100. The duration of the unwantedcollection may vary depending on the row readout time. The maximum timemay be one frame readout duration. However, a 5 percent leakage may leadto an intolerable 50 percent smear. In addition, extra pixel circuitelements and the in pixel storage, may take up real estate on the chip,and hence reduce the quantum efficiency of the system. Read noise mayalso be a problem.

[0022] A special pixel architecture is described herein that addressesthese issues and may improve the pixel efficiency. The pixelarchitecture as described herein may produce a barrier field, e.g.,based on electrical potentials, around the pixel storage area. Thebarrier field may prevent or discourage photoelectrons from theadjoining areas, e.g., the substrate and photodiode, from entering thepixel storage area.

[0023] In an embodiment, capacitor 115 may be implemented with aper-unit-area-capacitance that may be many orders of magnitude higherthe capacitance per unit area for the photodiode 100, e.g., it may be 2orders of magnitude higher. This may enable reduction of the storagecapacitance size, and reduce noise. In addition, there may be minimal ifany effect on the fill factor. For similar reasons, the quantumefficiency may be improved. This pixel architecture may also allowphotodiode implementation with a high collection efficiency in order toimprove quantum efficiency.

[0024] The pixel architecture is represented by the cross-section shownin FIG. 2. A twin well process with a lightly doped epitaxial layer isused. The twin well process includes an n well 200 and a P well 205.Both the N well 200 and the P well 205 are formed in a P type epitaxialsubstrate 210 formed on the P++ substrate 215. The P well 200 acts as aphotodiode. A storage capacitance 222 may be implemented in the P well205. The storage capacitance may be implemented as a diffusioncapacitance or as a gate capacitance. A transfer gate 200 is providedbetween the photodiode 218 and the storage capacitance 222. The transfergate 220 may be driven by the share switch 130 in FIG. 1. Both thephotodiode 218 and the storage capacitance to hundred 222 may beimplemented as n++ regions within the wells.

[0025] A metal shield 230 may be located over the storage node 222, andmay operate to maintain the integrity of stored photocharge in thestorage node 222. In addition, a potential well may be introduced aroundthe storage node 222. The storage node is located in the P. well 205,and this P. well may be held at ground potential. The other wells aroundthe P. well, including the P. type epitaxial well 210, and the N well200, may be biased above ground. Therefore, electrons generated ineither of these wells may be prevented from reaching the storage node222 by the potential barrier that is directed around the storage node.Moreover, the N++ area forming the storage node 222 within the P. wellis effectively reverse biased. Because of this reverse bias, no holeswill reach the storage node 222. The holes will rather be drained outthrough a P++ contact layer that is within the P. type well 200. Thiseffectively protects the storage node against coupling from thephotodiode, and thus allows smearless imaging.

[0026] The total capacitance of the photo site C_(d) is defined by thesum of the capacitance of the photodiode, and the capacitance of the n++region within the well. The doping of the epitaxial layer 210 may bevery small. This may cause the diode capacitance C_(P) to be very smallalso, e.g. <1 fF. Therefore, the per-unit area capacitance for thecapacitor 115 may be much larger than the per-unit area capacitance forthe photodiode, e.g., an order of magnitude larger, or two orders ofmagnitude larger. As such, the capacitor 15 may take up only a verysmall fraction of the area of the cell, and as such may have minimaleffect on the fill factor of the device.

[0027] The value of the photodiode capacitance is determined primarilyby the capacitance of the n++ implant in the n well 200 and the P well(to the left of the transfer gate). This allows the capacitance of thephotodiode and the capacitance of the capacitor to be changed over arelatively large range in order to optimize the noise withoutextensively affecting the imager's quantum efficiency.

[0028] There may be an optimum value for the value C_(P), thecapacitance of the capacitor 115. This optimum value may be governed byread noise considerations. Read noise in a photodiode based snapshottype active pixel sensor is substantially primarily governed by thenoise at the pixel. This noise at the pixel may include both photodiodeand storage capacitance reset noise as well as charge sharing noisecause during transfer of charge from the photodiode to the storagecapacitance.

[0029] If the charge of Δq_(D) is accumulated on C_(D) during one frame,and only a fraction of that charge is transferred to the in pixel framestorage capacitor C_(P) after charge sharing, the amount of charge addedto C_(P) is given by: $\begin{matrix}{{\Delta \quad q_{p}} = {{\frac{C_{p}}{C_{d} + C_{p}} \cdot \Delta}\quad q_{d}}} & (1)\end{matrix}$

[0030] The conversion gain is defined as the potential change on thesensing or storage node due to the photocharges: $\begin{matrix}{\frac{\Delta \quad V_{sense}}{\Delta \quad q_{d}} = \frac{1}{C_{d} + C_{p}}} & (2)\end{matrix}$

[0031] The sharing of signal between C_(P) and C_(D) may cause anattenuation in the desired signal. The charge handling capacity may begoverned by the amount by which the photodiode can actually swing. Ifthe total swing on the photodiode is defined by the valueV_(diode, Max), then the charge handling capacity may be given by

q _(d,max) =C _(d) ·V _(diode,max)   (3)

[0032] Another issue is raised by read noise. If the noise added in thepixel source follower or in the other electronics of the image sensor isexcluded, then read noise is basically from three sources. First, readnoise may be caused from the reset noise at C_(P) that is associatedwith resetting C_(P). Read noise is also caused from C_(D), again withnoise associated with resetting C_(D). The noise may also be caused byuncertainties created by charge sharing between C_(P) and C_(D). Thisuncertainty may be considered as: $\begin{matrix}{{{\langle{\Delta \quad q_{m}^{2}}\rangle} = {\left. {{{kT} \cdot \left( \frac{C_{d} + C_{p}}{C_{p}} \right)^{2} \cdot \left\lbrack {C_{p} + \frac{C_{p} \cdot C_{d}}{C_{d} + C_{p}}} \right\rbrack} + {{kT} \cdot C_{d}}}\Rightarrow\ldots \right.\quad = {\left. {{kT} \cdot \left\lbrack {C_{d} + \frac{\left( {C_{d} + C_{p}} \right)^{2}}{C_{p}} + {\frac{C_{d}}{C_{p}} \cdot \left( {C_{d} + C_{p}} \right)}} \right\rbrack}\Rightarrow\ldots \right.\quad = {{kTC}_{d} \cdot \left\lbrack {1 + {\left( \frac{1 + \alpha}{\alpha} \right) \cdot \left( {2 + \alpha} \right)}} \right\rbrack}}}}{{{where}\quad \alpha} = \frac{C_{p}}{C_{d}}}} & (4)\end{matrix}$

[0033] The inventors have plotted this function, which is shown as FIG.3. It is observed that the noise increase over a conventional photodiodeimplementation may reach a minimum of around 3 at a value α=0.9.Furthermore, by incorporating transistors, and the capacitance CP in thepixel, the fill factor may be reduced, thus lowering the responsivity ofthe pixel. When this is compared with an active pixel sensor with thesame photodiode capacitance, the effective responsivity reduction istherefore: $\begin{matrix}{\left\lbrack {1 + {\left( \frac{1 + \alpha}{\alpha} \right) \cdot \left( {2 + \alpha} \right)}} \right\rbrack \cdot \left( {1 + {\lambda \cdot \alpha}} \right)} & (5)\end{matrix}$

[0034] where λ is a factor expressing the effect of fill factor loss. Ifλ is zero, then there is no impact on the fill factor. If λ is 1, thenthe effective frame storage capacitance or C_(P) per-unit area is thesame as that for the photodiode. FIG. 3 shows the different values, andshows how the effective response reduction factor may be optimum when αis between 0.7 and 1. For small values of α, the gain loss due to chargesharing at the pixel may be significant and may lead to loss ofresponsivity. For values of α that are too large, the reset noise atC_(P) becomes larger then the reset noise at CP during the non snapshotmode of operation. The fill factor loss may also cause an additionalresponse loss. Hence, or larger α, response reduction may increase.

[0035] Another advantage is that, In spite of charge sharing, smear-freesnapshot imaging is obtained without sacrificing full-well. This is thecase since full-well is determined not by the diode voltage swing, butby the swing of the pixel source follower. Since optimally thecapacitance ratios are nearly equal, and since source-follower signalswing is half the voltage swing of the diode, no loss of full-well isencountered.

[0036] Another aspect obtains smear free snapshot imaging is obtainedwhile eliminating spurious noise and image lag using a dummy pixel row.In addition to read noise minimization, an issue may be raised by imagelag and signal dependent noise (spurious noise). Image lag and signaldependent noise arises due to variations in the reset levels on thediode (C_(D)) and the storage capacitance (C_(P)). In general, whenRST-C and RST-D are pulsed, capacitors C_(D) and C_(P) are charged todifferent values based on their initial conditions (e.g. the signal inthe previous frame). In order to eliminate image lag and spurious noise,the pixel can be preset before reset. Presetting forces the initialconditions of all the pixels to be substantially identical, irrespectiveof signal strengths in the previous frame, and hence eliminates bothspurious noise and image lag.

[0037] The preset level is determined by the current flow in the columnbus (through the pixel source-follower). For snapshot imaging, the diodeand storage capacitance is reset at different times. In fact, most oftenthe diode capacitance is reset without disturbing the storagecapacitance. However, only the storage capacitance, and not the diodecapacitance is not directly connected to the pixel source follower.Hence, this architecture poses problems for presetting the diode, sincepresetting requires current flow in the source follower. In ourapproach, this is circumvented by adding an additional dummy row ofpixels which is activated every time a pixel diode (or all pixel diodes)are preset and reset. This ensures that every diode and storagecapacitance is always reset to the same potential, eliminating spuriousnoise and image lag. In this scheme, elimination of these two effects isaccomplished without adding any hardware inside the pixel itself,thereby preserving high quantum efficiency. Hence, the pixelarchitecture is compatible with high quantum efficiency, minimum readnoise, high linearity, and no or minimal image lag or spurious noise.

[0038] Although only a few embodiments have been described in detailabove, other modifications are possible. All such modifications areintended to be encompassed within the following claims, in which:

1. A photosensor element, comprising: a photosensor, located to receiveincoming light, and to create photo carriers based on said incominglight, said photosensor having a first capacitance per-unit area; and astorage capacitance, selectively coupled to said photosensor, and havinga second capacitance per-unit area which is at least two orders ofmagnitude larger than the first capacitance per unit area of thephotodiode.
 2. An element as in claim 1, further comprising acontrollable gate, coupled between said photosensor and said storagecapacitance, which is selectively actuated to transfer a signal fromsaid photosensor to said storage capacitance.
 3. An element as in claim1, further comprising a light shield element, located to shield saidstorage capacitance against incoming light.
 4. An element as in claim 1,further comprising a reset structure, which operates to reset values insaid photosensor and said storage capacitance, based on applied controlsignals.
 5. An element as in claim one, wherein said photosensor has acapacitance C_(P), said storage capacitance has a capacitance C_(D), anda value α is defined as C_(P)/C_(D), and wherein said value α is >0.7.6. An element as in claim 5, wherein said value α is >0.9.
 7. An elementas in claim 1, wherein said second capacitance per-unit area is at leastten times greater than said first capacitance per-unit area.
 8. Anelement as in claim 1, wherein said photosensor includes a photodiode.9. An element as in claimed 8, further comprising a semiconductor regionforming an n well, holding said photodiode, and a second semiconductorregion forming a P well, holding said storage capacitance.
 10. Anelement as in claim 9, further comprising a P type lightly dopedepitaxial layer, underlying both said first semiconductor region andsaid second semiconductor region.
 11. An element as in claim 9, whereinsaid photodiode is formed as an N++ region within said n well, and saidstorage capacitance is formed as an N++ region within said P well. 12.An element as in claim 11, further comprising a transfer gate, formed onthe semiconductor substrate, and extending between the first N++ regionand the second N++ region.
 13. An element as in claim 9, furthercomprising a metal shield, formed over at least a portion of said P welland shielding said storage node against incoming light.
 14. An elementas in claim 9, further comprising a bias applied to said P. well thatprevents photo carriers from reaching said storage node.
 15. An elementas in claim 14, wherein said bias includes grounding said P well, andholding said N well at a bias above ground.
 16. An imaging device,comprising: a semiconductor substrate; a photodiode, formed in saidsemiconductor substrate, and having a capacitance C_(D); a selectiveconnection between said photodiode and a reset node; a storagecapacitance, formed in said semiconductor substrate, and having acapacitance C_(P); a second switch, selectively connecting said storagecapacitance to a reset node; and a third switch, connected between saidphotodiode and said storage capacitance, and selectively actuated toprovide photocarriers from said photodiode to said storage capacitance,wherein said photodiode and said storage capacitance are formed suchthat a ratio α=C_(P)/C_(D) is >0.7.
 17. An imaging device as in claim16, wherein said third switch includes a transfer gate.
 18. An imagingdevice as in claim 16, further comprising a light shield, covering saidstorage capacitance.
 19. An imaging device as in claim 16, wherein saidratio α is >0.9.
 20. An imaging device as in claim 16, furthercomprising a bias element providing an electrical shield to cover saidstorage capacitance against photoelectrons.
 21. An imaging device as inclaim 20, wherein said bias element includes biasing a semiconductorarea holding the photodiode at a higher level then a bias of thesemiconductor area holding the storage node.
 22. An imaging device as inclaim 20, wherein said biasing element biases the semiconductor areaholding the storage node to ground, and biases the semiconductor areaholding the photodiode to a level above ground.
 23. An imaging device asin claim 20, wherein said bias element includes reverse biasing asemiconductor element forming said photodiode to prevent holes fromreaching said photodiode.
 24. An imaging device as in claim 23, furthercomprising a contact located to drain holes away from said storagecapacitance.
 25. An imaging device as in claim 21, wherein thesemiconductor area holding the photodiode is a separate well from thesemiconductor area holding the storage node, the two wells havingopposite doping types.
 26. An imaging device as in claim 25, furthercomprising an epitaxial layer, on which the semiconductor areas holdingthe photodiode and the semiconductor area holding the storage node areboth formed.
 27. An imaging device as in claim 26, wherein saidepitaxial layer is lightly doped to P type, said semiconductor areaholding the photodiode is an N type well, and said semiconductor areaholding the storage node is a P type well, and wherein said P type wellis held at ground potential.
 28. An imaging device as in claim 27,wherein a capacitance per-unit area of said storage node is at least twoorders of magnitude higher than a capacitance per-unit area of saidphotodiode.
 29. An imaging device as in claim 16, wherein a capacitanceper-unit area of said storage node is at least two orders of magnitudehigher than a capacitance per-unit area of said photodiode.
 30. Animaging device as in claim 29, further comprising a plurality ofadditional photo sensors, forming an array of photo sensors.
 31. Aphotosensor, comprising: a first substrate doped to with a P++ dopingtype; a P. type epitaxial layer, lightly doped with P type impurities,formed on top of said P++ substrate; an active semiconductor area,located on said P type epitaxial layer, and including an N type wellholding a photodiode therein as an N++ type section within said N well,and a P type well, holding a storage node therein, as an N++ typeportion within the P type well, and a transfer gate, extending betweensaid N++ type photodiode, and said N++ type storage node, wherein acapacitance per-unit area of said storage node is much greater than acapacitance per-unit area of said photodiode.
 32. A photosensor as inclaim 31, wherein said capacitance per-unit area of said storage node isat least two orders of magnitude greater than the capacitance per-unitarea of said photodiode.
 33. A photosensor as in claim 32, furthercomprising defining a ratio between a capacitance of said storage nodeand a capacitance of said photodiode, and wherein said storage node andsaid photodiode are formed to maintain said ratio >0.7.
 34. Aphotosensor as in claim 31, further comprising a shielding element,located on top of said storage node, to shield said storage node againstreception of incoming light.
 35. A photosensor as in claim 31, furthercomprising a bias connection that provides a field around said storagenode that prevents photo carriers in adjacent areas from entering saidstorage node.
 36. A photosensor as in claim 35, wherein said field isformed by holding said P well at a lower bias than a bias of said Nwell, and said P. type epitaxial layer.
 37. A photosensor as in claim35, wherein said photocarriers include at least photoelectrons andholes.
 38. A method, comprising: forming an array of photodetectorelements, including a plurality of pixels, forming each pixel includinga photodiode in a first semiconductor area, and forming a storage nodefor said photodiode in a second semiconductor area, separate from saidfirst semiconductor area; operating said photodiode and storage node ina snapshot mode, where all pixels are sampled from said photodiode tosaid storage node at the same time; and biasing said storage node in away that prevents photo carriers from outside said storage node fromentering said storage node.
 39. A method as in claim 38, wherein saidbiasing prevents photo electrons from entering said second semiconductorarea.
 40. A method as in claim 38, wherein said biasing prevents holesfrom entering said storage node.
 41. A method as in claim 40, furthercomprising an electrode that draws holes away from said storage node.42. A method comprising: reading all pixel values in an imaging devicesimultaneously into respective in-pixel storage devices; and In eachsaid pixel, erecting both optical and diffusion shields for the in pixelstorage devices.